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Intel reveals Hewitt Lake processor family for internet of things

There is more to the conference as it is known as Mobile World Congress than smartphones. Take Intel's MWC Barcelona announcements, for example – they're a bit more infrastructural in nature. The Santa Clara chipmaker today debuted a new system-on-chip for edge devices and a field programmable gate array (FPGA) – the N3000 Programmable Acceleration Card (PAC).

The abovementioned edge chip, code-named "Hewitt Lake," slots into Intel's existing Xeon D 64-bit multicore microserver family, and promises improvements to both power efficiency and performance for network edge and storage solutions. Xeon D-1500 NS – a 14-nanometer product family launched in 2015 ̵

1; and while details were hard to come by, Hewitt Lake will presumably feature an integrated platform controller hub (PCH), a

Meanwhile, FPGA Programmable Acceleration Card (PAC) N3000, dubbed "Vista Creek," is a 1/2 length, full-height, dual-slot PCIe card optimized for custom vRAN and core solutions. Its internal hardware – which includes 1.1 million logic elements, 9GB of DDR4 memory and 144MB of QDR IV memory, and two XL710 network adapters for packet processing – drives virtualized workloads up to 8 x 10Gbps and 4 x 25Gbps, Intel says. The company is pitching it as a processing solution for 5G radio access networks, core network apps, and more.

The N3000 is expected to be available in the third quarter of 2019.

In addition to the Hewitt Lake and the N3000, Intel today announced that it would partner with Ericsson and ZTE to embed Intel's Snow Ridge's 5G base station designs. It also said that it is working with Skyworks to optimize the 5G RF solution for its XMM 8160 modem, and with Fibocam, a M.2 module manufacturer, to build its 5G modem into Fibocam's forthcoming FG100 product .

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