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Leaked AMD documents reveal new Zen 3 details

Eagerly awaited: Although a Zen 3 announcement is coming in, we will get some key details ahead of the October announcement thanks to leaked developer documents. While this leak doesn’t cover the whole picture of what Zen 3 will look like, it suggests it should be another strong line of CPUs for AMD with lots of generational improvements.

Allegedly confidential documents have been leaked by Twitter user CyberPunkCat that contain details of changes to Zen 3 that ship with the Ryzen 4000 desktop series with the code “Vermeer”.

We know AMD will finalize Zen 3 in October and the details in the documents repeat some things we already know while offering new information. The document appears to be a Processor Programming Reference (PPR) for AMD̵

7;s 19h Family, Model 21h B0, which would be Zen 3. Earlier Zen + and Zen 2 architectures belong to AMD’s 17h family with different models and revisions.

AMD typically makes this type of documentation available to developers after launch, so it isn’t exactly privileged information. In addition, such developer documents are usually easy to distribute – just ask Intel.

The most notable changes to Zen 3 seem to be in the CCD / CCX configuration. Zen 3 will continue to use an MCM (multi-chip module) or chiplet design that uses two CCDs and an I / O chip. There will only be one CCX per CCD, and this CCX consists of eight cores that can run in either single-thread mode (1T) or two-thread SMT mode (2T). So that’s a total of 16 threads per CCX.

This could suggest that 16-core Zen 3 parts are being padded in the same way as the Ryzen 9 3950X. However, we’ll have to wait and see if AMD might have some tricks up its sleeve.

In addition, AMD is revising its cache subsystem. A total of 32 MB L3 cache (as opposed to 16 MB per CCX with Zen 2) is distributed across all eight cores in the CCX. While Zen 2 offered 32MB of L3 cache per CCD, it had to be shared by two separate complexes. There is also 512KB of L2 cache per core within the CCX for a total of 4MB of L2 cache per CCD.

Interestingly, AMD is also improving the Scalable Data Fabric (SDF), the communications backbone of Infinity Fabric, which is responsible for data transport and coherence between cores, storage controllers, and other I / O elements. The documents indicate that the SDF can now handle 512 GB per DRAM channel. It looks like there could be some minor changes to the Scalable Control Fabric (SCF) as well, the other half of the Infinity Fabric that does mostly signaling.

Elsewhere, Zen 3 appears to fill the memory interface with two Unified Memory Controllers (UMC), each supporting one DRAM channel and each channel supporting two DIMMs. It will also support DDR4-3200 which was natively supported by Zen 2. It looks like Zen 3 will largely retain the same features and connectivity for the Fusion Controller Hub (FCH) that were present in Zen 2.

In addition to some generational clock glitches, Zen 3 appears to be further enhancing AMD’s MCM approach, focusing on improving coherence and latency under the hood. We also expect a measurable IPC improvement over Zen 2 parts.

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